The present invention relates to a static logic circuit and, more particularly, to improvements in a static logic circuit suitable for application to large-scale semiconductor integrated circuits.
Generally, a static logic circuit is constructed by connecting a plurality of logic gates comprising static operation type transistors for logical operation in a cascade connection. Each logic gate comprises a plurality of pairs of logic transistors having control terminals connected to each other to form input terminals, grounding current paths, i.e., current paths between output and ground terminals, each formed by connecting the other two terminals of one of the pair of transistors between an output terminal and a ground terminal in a series connection, a parallel connection or a series-parallel connection, and supply current paths, i.e., current paths between output and voltage supply terminals, each formed by connecting the other two terminals of the other one of the pair of transistors between an output terminal and a voltage supply terminal in a series connection, a parallel connection or a series-parallel connection. Each logic gate makes one of the grounding current path and the supply current path conductive and the other nonconductive according to the level of an input signal applied to the input terminal of the pair of transistors.
CMOS (complementary metal oxide semiconductor) logic circuits, which are typical static logic circuits, are widely used logic circuits because a supply current flows through CMOS logic circuits only when the input signal changes and no supply current flows through the same until the next change of the input signal and hence there is less power consumption with CMOS logic circuits (Kan M. Chu, et al., "A Comparison of CMOS Circuit Techniques", IEEE, Vol. SC-22, No. 4, pp. 528-532, August 1987).
The current drive ability of the pMOS transistor of a CMOS transistor used as a logical element in a CMOS logic circuit is about half that of the nMOS transistor of the same size. Therefore, the pMOS transistor is formed in an area about twice that of the nMOS transistor to equalize their current drive abilities so that the rise time and the fall time of the output signals are within an allowable range. Consequently, the parasitic capacitance of the pMOS transistor, principally junction capacitance, i.e., static capacitance parasitic on the drain electrode or the source electrode and gate capacitance, is about twice that of the nMOS transistor and the large parasitic capacitance of the pMOS transistor reduces switching speed. The reduction of the parasitic capacitance and the enhancement of the current drive ability conflict with each other; the current drive ability is reduced when the parasitic capacitance is reduce to enhance the switching speed, and the parasitic capacitance increases when the current drive ability is enhanced. Since the CMOS logic circuit needs the same number of pMOS transistors having a circuit area about twice that of nMOS transistors as that of nMOS transistors, it is difficult to form the CMOS logic circuit in a less circuit area. A method proposed in JP-A No. 2-277315 proposed as a means for improving the switching speed of a CMOS logic circuit connects a precharging MOS transistor to the output terminal. This method of improving the switching speed of a CMOS logic circuit is intended to control the rise and fall of a signal on the output terminal by charging and discharging according to a clock signal. However, there is the possibility that the logic MOS transistor becomes conductive during a precharging period and a high current flows through the transistor across the voltage supply terminal and the ground terminal. Therefore, the CMOS logic circuit needs a MOS transistor to prevent the current in addition to the precharging MOS transistor, which further increases the circuit area. Furthermore, the effect of this method in enhancing the switching speed is not satisfactory because the transistor for preventing the current increases the resistance of the circuit and repetition of charging and discharging in each clock period increases power consumption significantly.